1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same which are capable of reducing a short channel effect which causes a decrease in a threshold voltage in the semiconductor such as an FET (Field Effect Transistor).
2. Description of the Related Art
When a semiconductor device such as a MOS (Metal Oxide Semiconductor) transistor is scaled down, a so-called scaling law is used as an index. However, it is impossible to lower a supply voltage to meet the scaling law due to a need for considerations to be given to the supply of power to other semiconductor devices, which, as a result, causes impact ionization in which an electron and a hole are generated because of collision of a hot carrier having high energy caused by a high voltage within a channel region between a source and a drain with a lattice of the semiconductor device within a channel region. That is, this causes a so-called “hot carrier effect” in which a threshold voltage (Vth) is changed due to a fixed charge accumulated in a gate insulator of the MOS.
To solve this problem, a device having an LDD (Lightly Doped Drain) structure to reduce the generation of hot carriers is proposed. In such the device having the LDD structure, a region providing a low impurity concentration is formed which is placed in contact with each of a pair of impurity regions for a source and a drain and has the impurity concentration being lower than that in each of the pair of impurity regions and extends in a channel extending direction from each of the corresponding impurity regions. The region having the low impurity concentration limits an electric field existing in the vicinity of the drain and the generation of the hot carriers is reduced by the electric field limiting effect.
A method for forming a semiconductor device having such the LDD structure is disclosed in Japanese Patent Application Laid-open No. Hei 5-315355 in which the pair of the impurity regions to be used for the source and drain is formed by using a thermal diffusion method and each of the impurity regions having the low impurity concentration and extending from each of the impurity regions for the source and drain is formed by using ion implantation method. Moreover, a method is disclosed in Japanese Patent Application Laid-open No. Hei 5-153612 for forming both the pair of the impurity regions to be used for the source and drain and the low concentration impurity regions extending from each of the impurity regions to be used for the source and the drain, by using the ion concentration method.
In the conventional method, the extended impurity regions each extending from each of the pair of the impurity regions to be used for the source and the drain toward the channel direction are formed by using the ion implantation method.
Therefore, in the conventional technology, since the impurity region is formed by the ion implantation method, its impurity distribution shows that the impurity concentration is not lowered gradually from a surface of the device, but it becomes increased at a predetermined depth from the surface and exhibits its maximum level at the predetermined depth and then becomes decreased as the depth from the surface becomes larger.
The impurity distribution in the impurity region formed by the ion implantation in which the maximum impurity concentration is exhibited at the predetermined depth from the surface shows that the short channel effect produced at a position being lower than the surface is reduced as a result. As described above, the short channel effect causes the decrease in the threshold voltage and also causes a so-called punch-through phenomenon in which a voltage between the source and drain cannot be controlled by the gate voltage.